Advances in fabrication technology have resulted in high transistor counts and a high degree of integration of functions in ICs. However, this increased computational capability has an associated increase in capability for power consumption.
For mobile devices that are battery operated, such as cell phones, it is desirable to minimize power consumption in order to extend battery life. Control of power dissipation is also desirable in devices with high density ICs, mobility notwithstanding, in order to avoid operational instability and thermal damage.
For purposes of power consumption analysis, a logic IC may be viewed as a network of resistances and capacitances as a first approximation. The power dissipation in a logic IC is proportional to the product of the capacitance (C), square of the operating voltage (V2), and the operating frequency (f): P∝CV2f.
Since the capacitance associated with in IC is largely fixed by the design and fabrication process, the operating voltage and operating frequency are typically the focus for power management.
The time needed for the propagation of a signal within an IC varies with the signal path, and the time required for propagation along the slowest path typically places an upper limit on the operating frequency of an IC at a given voltage. Also, the maximum operating frequency is directly proportional to the operating voltage since an increase in voltage results in faster switching of the transistors in the IC.
In order to provide reliable operation, the operating frequency and operating voltage are typically selected so that signal will propagate along a critical path in a time that is shorter than the maximum allowable time. The difference between the actual operational propagation time and the maximum allowable for proper operation is referred to as “slack”. The slack in a circuit or subcircuit is dependent upon the operating frequency and voltage.
Typically, slack may be determined a priori by modeling techniques, and a table of safe operating frequency and voltage combinations may be developed for power management. However, since the frequency and voltage combinations are based upon a model, and must allow for model errors and fabrication process variations, the voltage reduction that is associated a given frequency reduction does not provide an optimal reduction in power consumption.
What is needed is a method for accurate determination of slack in an integrated circuit that accommodate fabrication process variations and avoids modeling errors. It is also desirable that the system be efficient and require a minimum amount of substrate area for implementation.